(1) Field of the Invention
The invention relates to an integrated circuit device, and, more particularly, to a built-in self test circuit for an embedded memory in an integrated circuit device.
(2) Description of the Prior Art
Embedded memory is an essential building block in many system on chip (SOC) integrated circuit devices. Such devices may combine a central processor function, signal processing, I/O and perhaps both nonvolatile memory and RAM. Of particular importance to the present invention is the presence of a large RAM array embedded in the integrated circuit and the challenges inherent in testing this embedded memory.
Typically, a stand-alone RAM device is tested using an automated, integrated circuit tester. The tester is connected to the I/O pins of the RAM. All of the memory locations within the memory can be easily addressed, written, and read to verify functionality. In this respect, several types of functional test patterns may be used to fully exercise the memory and to detect several types of potential faults. Techniques to detect “stuck at” faults, such as nodes stuck at ‘0’ or stuck at ‘1’ are well known in the art. Further, some patterns are particularly useful for detecting interactions between memory cells where a manufacturing defect causes the write state of a first cell to cause an error in the read state of a second cell. Comprehensive testing and error mapping of the stand-alone memory device is performed using such complex test patterns. The ability to fully access the memory using the available I/O pins allows such testing to be performed in a straightforward manner.
When such a memory array is embedded in a SOC integrated circuit device, the address, data, and control pins of the memory are not typically available to the automated tester. This is particularly true for the final, packaged device. The available pins are assigned to functional uses for the SOC device in its system application. Further, it is typically not practical, from a cost standpoint, to provide the full array of I/O connections from the memory to the tester even at the wafer level test. In addition, it is very difficult to test such a device at the very high operating speed of the circuit. Therefore, it is difficult to perform a comprehensive, automated test on the embedded memory array. Yet, to achieve the high levels of reliability demanded by the customer, it is essential that the memory be fully tested.
To address the above-described problems, methods have been developed in the art to test the embedded memory arrays using circuits built into the SOC device. These circuits are commonly called built-in self test (BIST) circuits or memory BIST (MBIST) circuits. Referring now to FIG. 1, an exemplary integrated circuit device 10 comprising a MBIST circuit 30 is illustrated in block diagram form. The integrated circuit device 10, such as a SOC device, has an embedded memory array 20. This embedded memory 20 may be a RAM array. This memory 20 is written and read by an internal processing unit, not shown, using typical control signals 50 and 52, an address bus 54, and a data bus 56 and 60.
The memory BIST unit 30 is also coupled to the standard control 50 and 52, address 54, and data signals 56 and 60 of the memory. In this way, the MBIST 30 is a second accessing unit to the memory 20. When the device 10 is placed into a self-testing mode by an external, automated tester, the MBIST 30 accesses the memory 20 by controlling the write enable 50, the chip enable 52, address bus 54, and data in/out bus 56 and 60. The MBIST unit 30 comprises a pattern generator unit 38, a compare unit 34, and an optional error address and data storage unit 42. The pattern generator unit 38 executes a testing sequence by writing data to address locations in the embedded memory 20 and then reading these same address locations from the embedded memory 20. The read data from the memory data output 60 is compared to the written data 68 from the pattern generator unit 38 by the compare unit 34. If any of the bits of the data read 60 does not match the value from the pattern generator 38, then the compare unit 34 indicates an error 64 and 62. This error is accessible to the external, automated tester through the ERROR_FLAG output pad 46. If the error address and data storage unit 42 is used, then data in, data out, and address 58 information from the pattern generator unit 38 is stored in the unit 42. The stored version 66 of the address and data information is accessible via an output 66.
This technique can be used to functionally test the memory 20 as indicated by the pass/fail of the ERROR_FLAG. However, there are two serious limitations to this approach. First, the method does not distinguish between single or multiple errors in the memory 20. All fails look the same. Second, the method provides no mapping of where errors or defects are occurring in embedded memory 20. Therefore, while the method facilitates a pass/fail final test, it does not provide visibility into the extent or location of errors for fixing a manufacturing problem.
Several prior art inventions relate to built-in self test (BIST) methods and devices. U.S. Pat. No. 6,019,502 to Baeg et al describes a BIST circuit for testing an embedded function. A circuit provides error detection for the BIST signals. U.S. Pat. No. 6,367,042 B1 to Phan et al discloses a BIST circuit for an embedded memory. The circuit uses a comparitor to compare the expected memory data with the actual memory data. An error signal is generated and is used by a circuit to re-route failed address locations to redundant locations in the memory. U.S. Pat. No. 6,405,331 B1 to Chien teaches a method to perform a BIST on an embedded memory. The method implements a time division multiplex scheme to provide information on detected bad cells through a limited number of output pads to an external automated tester at a reduced clock rate. U.S. Pat. No. 6,505,313 B1 to Phan et al shows a BIST circuit for an embedded memory. U.S. patent application 20020194558 A1 to Wang et al describes a method and a design system for a BIST capable of testing multiple, embedded memories. Capability for diagnosing faulty address and data combinations is also described.